The Accelerator War – AWS Tranium, Google TPU, Habana Gaudi and Others

In my previous articles written in earlier this year, I have discussed AWS Tranium/ Inferentia （Marvell (MRVL US) vs. Alchip (3661 TT) – Who is the AWS ASIC Winner?）and Google TPU（ Celestica (CLS US) vs. Flex (FLEX US) – Who is the Google TPU Winner?）. Recently, with Marvell's strong earnings report and the upcoming Broadcom earnings, investors are showing increased interest in AWS and Google's ASIC chips. Therefore, I will address the following popular questions that investors are currently concerned about:

1. What is Marvell’s potential revenue from AWS ASIC in 2025? Will Tranium 2 really reach the rumored volume of ~4 million units?

2. Who will help design AWS Tranium 3/ Inferentia 3 chip? Can Alchip continue to see strong revenue growth in the coming years?

3. How long will the product transition period for Google TPU last? Can Broadcom significantly increase its AI ASIC revenue in 2025?

4. Who will produce Google TPU V7? What are the implications for Broadcom and MediaTek?

First, here are my key conclusions:

1. I estimate that the volume of Tranium 2 chips in 2025 will be approximately 1.7 million units, generating more than $3.4 billion in revenue for Marvell. The rumored ~4 million units likely stemmed from a misinterpretation of the number of active interposer dies as the number of Tranium 2 chips (the actual count should be halved).

2. Starting in 2025, AWS has decided to cancel all Inferentia chips, including Inferentia 2.5 and Inferentia 3. This means the third-generation ASIC chip from AWS will only be Tranium 3, developed in collaboration with Alchip. Mass production of Tranium 3 is expected to begin in Q3 2025. Based on Alchip’s 2025 CoWoS capacity reserved at TSMC, Tranium 3 could generate approximately $1 billion in revenue for Alchip in 2025, with a total lifecycle revenue contribution of over $4.5 billion.

3. Due to the transition from Google TPU V6e to V6p, Broadcom’s AI ASIC revenue (mainly from Google TPU) will experience a ~20% sequential decline in Q4 2024 or its FY Q1 2025. However, this product transition period will be short-lived, lasting only two quarters (Q4 2024 and Q1 2025). Growth will resume in Q2 2025 with the ramp-up of TPU V6p production. For FY2025, Broadcom’s AI ASIC revenue is expected to grow to ~$13 billion.

4. According to my supply chain research, Google’s next-generation TPU V7 will also have two versions. V7p will remain fully handled by Broadcom, while V7e will have its ASIC die designed by Google in-house team, with Taiwan’s MediaTek designing the I/O die. Mass production of V7e is scheduled to begin in Q3 2026, with a total lifecycle volume of approximately 2 million units, potentially generating over $6 billion in revenue for MediaTek.

Next, let me answer the above four questions in more details.

First, let’s take a look at the Tranium 2 chip that AWS showcased at its last week’s Re:Invent 2025 event. This is an ASIC chip based on CoWoS-R packaging, designed by Marvell (code name: Cayman). The entire chip consists of 2 ASIC dies, 4 HBM3 dies, and 2 active interposer dies (AIDs). Each interposer die has a size of approximately 1,200 square millimeters and hosts 1 ASIC die and 2 HBM dies. The two active interposer dies are then connected via RDL layers to form a complete Tranium 2 chip (see picture below). This approach of using multiple AIDs to piece together a complete accelerator chip was explained in detail when I discussed AMD’s MI300 structure in an earlier article（BESI (BESI NA) -- Where is Hybrid Bonding Used?）. Nevertheless, unlike AMD, which uses 4 AIDs, AWS employs only 2 AIDs.

In the following paragraphs, I will provide a detailed analysis of the following topics:

1. Marvell's quarterly CoWoS wafer volume and its corresponding production volume for Tranium 2/ Inferentia 2.5.

2. ASP and GPM of Marvell's AWS ASIC project, along with Marvell's estimated revenue contribution from AWS for 2024 and 2025.

3. Alchip's quarterly CoWoS wafer volume and its corresponding production volume for Tranium 3 and Gaudi 3.

4. ASP of Tranium 3 and Gaudi 3, and estimated revenue contributions from AWS ASIC and Intel Habana projects to Alchip.

5. Broadcom's quarterly CoWoS wafer volume and its corresponding production volume for V6e/V6p.

6. ASP of Broadcom's TPU projects, along with Broadcom's estimated revenue contribution from Google TPU projects for 2025.

7. Future design of Google TPU V7e/V7p, the production timeline, and the potential revenue contribution to MediaTek.